----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    17:51:18 08/19/2014 
-- Design Name: 
-- Module Name:    TrigIn - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity TrigIn is
    Port ( clk_in : in  STD_LOGIC;
           ce_in : in  STD_LOGIC;
           trig_in : in  STD_LOGIC;
           reset_in : in  STD_LOGIC;
			  en_in : in  STD_LOGIC;
           out1 : out  STD_LOGIC);
end TrigIn;

architecture Behavioral of TrigIn is
signal locOut : STD_LOGIC := '0';
begin

	process(clk_in, ce_in, en_in, reset_in, trig_in)
	begin
		if (reset_in = '1') then
			locOut <= '0';
			
		elsif (clk_in'event and clk_in = '1' and ce_in = '1' and trig_in = '1' and en_in = '1') then
			locOut <= '1';
		end if;
	end process;
	
	out1 <= locOut;

end Behavioral;

